FIG. 3 shows, in cross-section, the main part of a fundamental field effect transistor (hereinafter referred to as an FET). In FIG. 3, reference numeral 1 designates a semiconductor substrate. Conductive layers or insulating layers required for operation are disposed on the substrate 1. A gate electrode 2 is provided to modulate the current flowing from the drain electrode 3 to the source electrode 4 in response to an electrical signal applied thereto.
One use of such an FET is as a low noise amplifier. The characteristic which is most important in this use is the noise figure (hereinafter referred to as NF) which indicates the noise level generated by the FET itself. Since the noise figure deteriorates with an increase in frequency, in order to use the FET at a high frequency, such as in microwave or millimeter wave frequencies, a variety of steps have to be taken. The minimum noise figure (NF.sub.min) is usually represented by the following formula: ##EQU1## where gm is transconductance, R.sub.s is source series resistance, R.sub.g is gate resistance, C.sub.gs is gate-to-source capacitance, K.sub.f is a constant, and f is the frequency. As is understood from the above formula, to reduce NF, an increase in the transconductance gm and reductions in the gate-to-source capacitance C.sub.gs, gate source resistance R.sub.s, and gate resistance R.sub.g are required.
To reduce C.sub.gs and increase gm, shortening of the gate length (L.sub.g) of the device is most effective. In GaAs MESFETs or HEMTs (high electron mobility transistor) which have been recently devised as low noise elements used at microwave frequencies, the L.sub.g is usually quite short, less than 0.5 micron. However, the shortening of L.sub.g invites a reduction of gate cross-sectional area and an increase of R.sub.g. For example, in the rectangular gate electrode as shown in FIG. 3, there is a limit to the reduction of NF. The value of NF.sub.min at 12 GHz is limited to about 1 dB.
The reduction of R.sub.g is accomplished by production of a T-shaped gate electrode as shown in FIG. 4. In FIG. 4, a gate electrode 2 has a T-shaped cross-section and the gate length L.sub.g, which is the length of the gate in contact with the semiconductor substrate 1, is quite narrow, i.e., 0.2 micron. However, the upper portion of the gate electrode has a larger cross-sectional area, thereby suppressing the increase in R.sub.g. By such a construction, an element having an NF.sub.min of 0.5 to 0.6 dB is realized, showing that the reduction of R.sub.g is quite effective. However, the production of T-shaped gate electrodes requires patterning of L.sub.g to about 0.2 micron, which is not easy.
FIG. 5 shows a plan view of an FET. Reference numeral 2a designates a gate finger and reference numeral 2b designates a gate pad. Reference numerals 3 and 4 designate a drain electrode and a source electrode, respectively. Reference numeral 5 designates a feeding point for applying a voltage to the gate finger 2a. FIGS. 3 and 4 correspond to cross-sections taken along lines III--III and IV--IV in FIG. 5. The external connection is made by adhering a wire to the gate pad 2b.
Usually, an FET element is constructed as shown in FIG. 5, and a voltage is applied from the two feeding points 5 to the gate finger 2a, and the length of the gate finger 2a (the entire gate width is W.sub.g) is electrically divided by four, thereby resulting in four unit gate widths, Z, each of which is equal to W.sub.g /4. There is a relationship between the gate resistance R.sub.g, entire gate width W.sub.g, and unit gate width (which is a feeding length from respective feeding points) Z, EQU R.sub.g .varies.W.sub.g Z.sup.2.
For a fixed gate width W.sub.g, it is useful to increase the number of feeding points 5 to shorten the unit gate width Z.
By increasing the number of feeding points, the increase of R.sub.g can be suppressed. However, if the number of feeding points is simply increased by a construction as shown in FIG. 5, the number of gate pads 2b is also increased and many external connections have to be made. Furthermore, an increase in the number of large area gate pads would unfavorably invite an increase in the floating capacitance.
FIGS. 6(a) and 6(b) show an example in which the number of feeding points is increased without increasing the number of gate pads. FIG. 6(a) shows a plan view and FIG. 6(b) shows a cross-sectional schematic view taken along line VIb--VIb of FIG. 6(a). The number of feeding points is five and the unit gate width Z is W.sub.g /10, whereby the R.sub.g is significantly reduced. The gate pad 2b and the feeding points 5 are connected by the gate wiring 6, and this gate wiring 6 crosses the source electrode 4. Of course, the gate wiring 6 and the source electrode 4 are electrically isolated from each other. However, care has to be taken not to increase the capacitance therebetween. Therefore, the gate wiring 6 is arranged bridging the source electrode 4. Such a structure is usually called an airbridge. Because air has a smaller dielectric constant than an insulating film, such as SiO.sub.2, it is possible to reduce the capacitance with an airbridge. The example shown in FIGS. 6(a) and 6(b) is disclosed in the IEICE Technical Report, Volume 88, Number 60, pages 39-44 (1988) and, in such a construction, an improved NF.sub.min of 0.5 to 0.6 dB is realized without using a gate having a T-shaped cross-section.
Another construction shown in FIGS. 7(a) and 7(b) reduces the gate resistance (European Patent 0,203,225, IEEE Transactions on Electron Devices, Volume ED-32, Number 12, December 1985, pages 2754-2759, "Airbridge Gate FET For GaAs Monolithic Circuits"). This construction employs an airbridge structure similar to that shown in FIG. 5. In this construction, electric power is not supplied at a point but along the entirety of the gate width. When such a construction is used, the R.sub.g can be reduced to a negligible value which is quite useful for low noise properties. However, the gate electrode 6 and the source electrode 4 cross each other over a large area, and eve if an airbridge structure is used, the increase in gate capacitance causes a large problem.
As discussed above, a variety of structures have been proposed to reduce the gate resistance in order to produce a low noise FET. However, the accompanying production processes are very difficult to apply in industrial fabrication or produce an increase of gate capacitance which unfavorably influences the FET characteristics. These problems result in an insufficient performance improvement.